Eye diagrams are a conventional format for representing parametric information about signals, and especially digital signals. Various prior art eye diagram testers are known, but we shall call the technique described in the two incorporated Applications, an Eye Diagram Analyzer, or EDA for short.
A modern eye diagram for a digital signal is not so much a trace formed continuously in the time domain, as it is an “eye” shape composed of closely spaced points (illuminated pixels) representing many individual measurement (time, voltage) samples taken upon separate instances of a signal occurring on a channel of interest, and which were then stored in a memory. Each measurement sample contributes to a displayed pixel. The eye shape appears continuous because the collection of pixels is rather dense, owing to the large number of times that the signal is sampled. Unlike a true continuous technique, however, there may be detached pixels that are separated from the main body of the eye shape.
In any event, the vertical axis is voltage, and the horizontal axis represents the differences in time (i.e.,various offsets) between some reference event and the locations for the measurement samples. The reference event is generally an edge of a clock signal in the system under test, represents directly or through some fixed delay the expected point in time when the value of an applied data signal would be captured by some receiving circuit in an SUT (System UnderTest), and is derived from an application of the SUT's clock to the Eye Diagram Analyzer. The time axis will generally have enough length to depict one complete eye-shape (cycle of a SUT signal) centered about the reference, with sometimes perhaps several additional eyes (cycles) before and after.
Different (X, Y) regions within a (sample) space containing an eye diagram represent different combinations of time and voltage. Assume that the eye diagram is composed of a number of pixels, and temporarily assume that the resolution is such that each different (X, Y) pixel position can represent a different combination of time and voltage (and vice versa), which combinations of time and voltage we shall term “measurement points.” What the Eye Diagram Analyzer measures is the number of times, out of a counted number of clock cycles, that the signal on the channel being monitored passed through a selected measurement point. Then another measurement point is selected, and the process repeated until there are enough measurement points for all the pixels needed for the display. Points along the visible eye diagram trace describe something about those (time, voltage) combinations that were observed to actually occur in the data signal under test. The value of a (time, voltage) combination is represented by its location, but the color or intensity of the measured result is determined in a way that assists in further appreciating the meaning of the measured data, such as how often a (time, voltage) point was occupied by the signal being measured. The range over which the measurement points are varied is called a “sample space” and is defined during a measurement set-up operation. And in reality, we define the sample space and the resolution for neighboring measurement points first, start the measurement and then let the analyzer figure out later how to ascribe values to the pixels of the display. The “display” is, of course, an arbitrary graphic output device such as a printer or an X Window of some as yet unknown size in a window manager (e.g., X11) for a computer operating system. (A one-to-one correspondence between display pixels and measurement points is not required. It will be appreciated that it is conventional for display systems, such as X Windows, to figure out how to ascribe values to the pixels for an image when the correspondence between the display's pixel locations and the measurements that are the original image description is not one-to-one.)
The EDA of the incorporated “METHOD AND APPARATUS FOR PERFORMING EYE DIAGRAM MEASUREMENTS” operates by applying the clock signal from the SUT to a comparator circuit whose output is then delayed by a fixed amount, say about a half cycle, or some integral multiple thereof. The delayed clock comparison is then the reference mentioned above, and it used in determining when individually threshold-compared and then delayed data signals (the SUT data channels) are sampled.
This sampling of the individually threshold-compared and then delayed data signals is actually performed twice in rapid succession, a very brief (but selectable) amount of time apart. If these two successive samples (which are comparisons to the same voltage!) are different, then the input signal made a transition through the voltage of interest, and we call this a hit. This manner of sampling is what we termed the “basic voltage measurement technique” in the Plan Of The Application, and it accomplishes the taking of the (time, voltage) pairs that are the basic data of the eye diagram measurement, and it is an alternative to digitizing with a conventional Analog-to-Digital Converter (ADC). We use it because it works at frequencies that are impractical for ADCs, and because there are often a large number (greater than one hundred) of channels to measure. ADCs are large and expensive in comparison to this basic voltage measurement technique.
In the original METHOD AND APPARATUS . . . technique, different sampling voltages are obtained by varying the comparison thresholds for the data signals. Different times are obtained by varying the amount of delay in the data channel path, while leaving the clock data signal path essentially fixed. Skew between data channels is removed by introducing corresponding increases or decreases in the individual delays of the data channels.
An advantage of this technique is that, once skew is calibrated out, it allows the delay and threshold comparison for each data channel to vary independently as needed to complete the measurement. That is, the EDA will dwell on a measurement point for say, a specified number of clocks, or say, until some other condition is met, before moving on to the next measurement point. It sometimes happens that the rate of progress among the channels is not all the same. Hence, the ability to have independent variation by channel allows a faster partial accumulation of the results, which can be viewed by the operator as they are obtained.
There is, however, a disadvantage to this eye diagram analyzer technique as set out in “METHOD AND APPARATUS FOR PERFORMING EYE DIAGRAM MEASUREMENTS”. The delay lines used are each a tapped series of non-inverting buffers. The input is applied to the start of the tapped series, and the delayed output is taken at the location in the series selected by the tap. It is important to remember that each buffer in the tapped sequence has a frequency response (finite rise and fall times), and that the combined effect for large values of delay (over a thousand buffers in series) is significant. The effective rise and fall time for the stage of delay at the final tap is considerably less than that for any single buffer in the sequence, and it can turn an Eye Diagram Analyzer into a Worm Diagram Generator as voltage comparison outputs propagating through the delay lines appear to become pulses that are either too short or too long, and then fail to properly activate the difference detection mechanism. (For brevity, we can't here do justice to the whole, and somewhat subtle, chain of cause and effect. Fortunately, we don't need to. Curious readers should consult the incorporated EYE DIAGRAM ANALYZER WITH FIXED DATA CHANNEL DELAYS AND SWEPT CLOCK CHANNEL DELAY). In any event, a cure for this is set out in that incorporated Application, even though it still continues to use the same basic voltage measurement technique.
FIG. 1 is a simplified block diagram 11 of the original (swept data channel delay) EDA technique. FIG. 2 is a simplified block diagram 12 of the alternate (swept clock channel delay) EDA technique. Observe that they both use the same mechanism to sample data channel voltage, which is the afore-mentioned technique of noticing that the output of a comparator has changed.
In particular, note that in FIG. 1 a variable SWEPT DATA SIGNAL DELAY 10 produces a voltage-compared data channel signal 2 that has been delayed by a variable amount according to what amount of delay in a cycle of swept amounts of delay is currently in effect. The signal 2 is applied to a D input of a latch 3 that is clocked by a clock signal 1, that while it has been delayed by a CONFIGURABLE CLOCK TRIM DELAY mechanism 9, may be thought of as being “the SUT clock”. The voltage-compared data channel signal 2 is also applied to the D input of another latch 4 that is clocked by a slightly delayed (by dt DELAY) version of the clock signal 1. The idea is that if the SUT data signal for that channel passed through the comparison threshold at a time corresponding to the current SWEPT DATA SIGNAL DELAY, then the two latches 3 and 4 will capture different values, which condition is detected by XOR gate 6 and used to increment a # OF HITS COUNTER 7. We call this mechanism a TRANSITION DETECTOR (8) or a QUANTIZED dv/dt DETECTOR.
In FIG. 2 there is a block diagram 12 of the swept clock channel delay technique, which, it will be appreciated from the figure, has the same TRANSITION DETECTOR (8) or a QUANTIZED dv/dt DETECTOR. In fact, the block diagrams 11 and 12 are seemingly identical, although they operate in different manners. What used to be a CLOCK TRIM DELAY 9 in FIG. 1 is now operated as SWEPT CLOCK DELAY 13 in FIG. 2, and what used to be SWEPT DATA SIGNAL DELAY 10 in FIG. 1 is now operated as DATA SIGNAL DE_SKEW DELAY 14.
It would be desirable for use in either EDA architecture if the voltage measurement mechanism were capable of detecting that a signal to be sampled was or was not, to within some agreeable tolerance, at a certain voltage, and to do so without relying solely on a transition through that certain voltage, so that a signal of the certain voltage will produce a hit even if is not in transition at the time of sampling. Why this would be a desirable improvement is explained as follows.
With both of the techniques of FIGS. 1 and 2 the reliance on detecting a transition through a certain threshold to decide upon a signal value at the time of sampling remains open to failure to detect a hit when the signal voltage does not aggressively transition at the time of the sample. The basic voltage sampling mechanism relies somewhat on noise in the signal and uncertainty in the comparator to cause hits along the top (exerted / not exerted) and baseline (not exerted I exerted) signal values. A perfectly clean noise-free signal having no dv/dt between its rise and fall, combined with an ideal comparator, would produce no hits except during the rise and fall. So we have a situation where, if the SUT's signals are really quite good and the measurement hardware is also really quite good, then the eye diagram goes away except at the transitions; it would seem that better is worse! So far, nobody's equipment is quite that good, but the notion of “better is worse” is a disgusting situation that needs to be foreclosed. What to do?